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copyright ? 2012 cirrus logic, inc. feb 2012 all rights reserved ds705f2 audio decoder dsp family with dual 32-bit dsp engine technology cs4953xx data sheet http://www.cirrus.com features ? multi-standard 32-bit audio decoding plus post processing ? supports legacy audio formats and a wide array of post- processing ? dolby digital ? ex, dolby pro logic ? ii, iix, iiz 7.1, dolby headphone ? 2, dolby virtual speaker ? 2, dolby volume ? (original), dolby volume 258 ? (lite), audistry ? ? dts-es 96/24 ? discrete 7.1, dts-es ? discrete 7.1, dts-es ? matrix 6.1, dts neo:6 ? , dts neural surround ? dts surround sensation speaker ? mpeg-2 aac ? lc 5.1 ?srs ? circle surround ? ii, srs circle surround auto, srs circle surround de coder optimized, srs truvolume ? 7.1 (v 2.1.0.0), srs trusurround hd/hd4 ? , srs wow hd ? , srs cs headphone ? , srs circle cinema 3d ? , srs studio sound hd ? ?thx ? ultra2 ? , thx select2 ? ? cirrus logic?s applications library ? cirrus original multi-c hannel surround 2 (coms2), cirrus band xpander ? , cirrus virtualization technology (cvt), cirrus intelligent room calibration 2 (irc2), cirrus bass enhancement (cbe) ? crossbar mixer, signal generator ? advanced post-processors including: 7.1 bass manager quadruple crossover, tone control, 11- band parametric eq, delay, 2:1/4:1 decimator, 1:2/1:4 upsampler ? up to 12 channels of 32-bit serial audio input ? 16 ch x 32-bit pcm out with dual 192 khz s/pdif tx ? two spi ? /i 2 c ? ports ? customer software security keys ? large on-chip x, y, and program ram & rom ? sdram and serial flash memory support the cs4953xx dsp family are the enhanced versions of the cs495xx dsp family with higher overall performance and lower system cost. the cs495 3xx includes all mainstream audio processing codes in on-chip rom. this saves external memory for code storage. in addition, the intensive decoding tasks of dolby digital surround ex ? , aac multi-channel, dts-es 96/24, thx ultra2 cinema and dolby headphone can be accomplished without the expense of external sdram memory. with larger internal memo ries than the cs495xx, the cs49531x is designed to support up to 150 ms per channel of lip-sync delay. with 150 mh z internal clock speed, the cs4953xx supports the most demanding post-processing requirements. it is also designed for easy upgrading. customers currently using the cs495xx can upgrade to the cs4953xx with minor hardware and software changes. ordering information see page 28 for ordering information. coyote 32-bit dsp a d m a coyote 32-bit dsp b ext. memory controller p s/pdif x y p x y serial control 1 16 ch pcm audio out serial control 2 parallel control gpio debug stc tmr1 tmr2 pll s/pdif 12 ch pcm audio in
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 2 table of contents 1 documentation strategy .... ................ ................ ................. ................ ................. ................ ......4 2 overview ................... ................. ................ ................ ................. ................ ............... .................4 2.1 migrating from cs495xx(2) to cs4970x4 ..................................................................................... ............ 5 2.2 licensing ................................................................................................................. ................................. 5 3 code overlays ............. ................ ................ ................. ................ ................. ................ .............5 4 hardware functional description ......... .............. .............. .............. .............. .............. .............6 4.1 coyote dsp core ........................................................................................................... .......................... 6 4.1.1 dsp memory .............................................................................................................. .................6 4.1.2 dma controller .......................................................................................................... ..................7 4.2 on-chip dsp peripherals ................................................................................................... ...................... 7 4.2.1 digital audio input port (dai) .......................................................................................... .............7 4.2.2 digital audio output port (dao) ......................................................................................... .........7 4.2.3 serial control port 1 & 2 (i 2 c or spi) ..........................................................................................7 4.2.4 parallel control port ................................................................................................... .................7 4.2.5 external memory interface ............................................................................................... ...........7 4.2.6 general purpose input/output (gpio) ..................................................................................... ...7 4.2.7 phase-locked loop (pll)-based clock generato r ......................................................................8 4.3 dsp i/o description .................................. ..................................................................... .......................... 8 4.3.1 multiplexed pins ........................................................................................................ ..................8 4.3.2 termination requirements ................................................................................................ ...........8 4.3.3 pads .................................................................................................................... ........................8 4.4 application code se curity ................................................................................................. ....................... 8 5 characteristics and specific ations ................ ................ ................. .............. .............. ............. 8 5.1 absolute maximum ratings .................................................................................................. .................... 8 5.2 recommended operating conditions ............. ............................................................................. ............ 9 5.3 digital dc characteristics ................................................................................................ ........................ 9 5.4 power supply characteristics .............................................................................................. .................... 9 5.5 thermal data (144-pin lqfp) ............................................................................................... ................ 10 5.6 thermal data (128-pin lqfp ) ............................................................................................... ................. 10 5.7 switching characteristics? reset ......................................................................................................... 11 5.8 switching characteristics ? xti ........................................................................................... ................. 11 5.9 switching characteristics ? internal clock .. .............................................................................. ............ 12 5.10 switching characteristics ? serial control port - spi slave mode ..................................................... 12 5.11 switching characteristics ? serial control port - spi master mode ................................................... 13 5.12 switching characteristic s ? serial control port - i 2 c slave mode ...................................................... 14 5.13 switching characteristic s ? serial control port - i 2 c master mode .................................................... 15 5.14 switching characteristics ? para llel control port - intel slave mode ................................................. 16 5.15 switching char acteristics ? parallel control port - motoro la slave mode ......................................... 18 5.16 switching characteristics ? digital audio slave input port ............................................................... .. 20 5.17 switching characteristics ? digital audio output port .................................................................... .... 21 5.18 switching characteristics ? sdram interface .............................................................................. ...... 22 6 ordering information ...... ................. ................ ................ ................. ................ ................ .......26 7 environmental, manufacturing, a nd handling information .............. ............... ........... .........26 8 device pin-out diagram .... ................ ................ ................. ................ ................. ................ ....27 8.1 128-pin lqfp pin-out diagram ...................... ........................................................................ ............... 27 8.2 144-pin lqfp pin-out diagram .................. ........................................................................... ............... 28 9 package mechanical drawings ......... ................ ................. .............. .............. .............. ...........29
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 3 9.1 128-pin lqfp package drawing .............................................................................................. ............. 29 9.2 144-pin lqfp package drawing .............................................................................................. ............. 30 10 revision history .......... ................ ................. ................ ................ ................. ............... ..........31 list of figures figure 1. reset timing ....... ................. ................ ................ ................ ................ ................ ................................12 figure 2. xti timing .......................................................................................................... ....................................12 figure 3. serial control port - spi slave mode timing ......................................................................... .................15 figure 4. serial control port - spi master mode timing ........................................................................ ................16 figure 5. serial control port - i2c slave mode timing ......................................................................... .................17 figure 6. serial control port - i2c master mode timing ........................................................................ ................18 figure 7. parallel control port - intel slave mode re ad cycle ................................................................. .............20 figure 8. parallel control port - intel slave mode wr ite cycle ................................................................ ..............20 figure 9. parallel control port - mo torola slave mode read cycle timing ....................................................... ....22 figure 10. parallel control port - motorola slave mode write cycle timing ..................................................... ....22 figure 11. digital audio input (dai) port timing dia gram ...................................................................... ...............23 figure 12. dai slave timing diagram ........................................................................................... ........................23 figure 13. digital audio port output timing master mode ....................................................................... ..............24 figure 14. digital audio output timing, slave mo de ............................................................................ .................25 figure 15. external memory interface - sdram burst read cycle ................................................................. ......26 figure 16. external memory interface - sdram burst write cycle ................................................................ .......26 figure 17. external memory interface - sdram auto re fresh cycle ............................................................... .....27 figure 18. external memory interface - sdram load mode register cycle ........................................................2 7 figure 19. 128-pin lqfp pin-out dr awing (cs495303/cs495313) ................................................................... ...30 figure 20. 128-pin lqfp pin-out dr awing (cs495304/cs495314) ................................................................... ...31 figure 21. 144-pin lqfp pin-out drawing (cs495313) ............................................................................ ............32 figure 22. 128-pin lqfp package drawing ...................................................................................... ...................33 figure 23. 144-pin lqfp package drawing ...................................................................................... ...................34 list of tables table 1. cs4953xx related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2. device and firmware selection guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. CS49530X dsp memory sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. cs49531x dsp memory sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. environmental, manufacturing, and handling information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. 128-pin lqfp package characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8. 144-pin lqfp package characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 4 1 documentation strategy the cs4953xx data sheet describes the cs4953xx family of multichannel audio decoders. this document should be used in conjunction with the following docume nts when evaluating or de signing a system around the cs4953xx family of processors. the scope of the cs4953xx data sheet is primarily the hardware specifications of the cs4953xx family of devices. this includes hardware functionality, char acteristic data, pinout, and packaging information. the intended audience for the cs4953xx data sheet is the system pcb designer, mcu programmer, and the quality control engineer. 2 overview the cs4953xx dsp family, together with cirrus logic?s comprehensive library of audio processing algorithms enables the development of next-generation audio so lutions. there are two classes of devices in the cs4953xx dsp family: ? cs4953x3 class (rom id 3), comprising the cs495303 and the cs495313 ? cs4953x4 class (rom id 4), comprising the cs495304 and the cs495314 the primary difference between the cs4953x3 and th e cs4953x4 classes is the support of the dsp condenser application on the cs4953x4 class of products only. the dsp condenser is a tool set that enables the dsp to automatically boot and conf igure itself from an external serial flash, thus reducing the traditional heavy loading on the part of the system microcontroller. because of the design time savings, enhanced tools support, and better performance associated with the cs49 53x4 product set, cirrus logic recommends that the cs4953x4 family be used for all new designs. more information on the dsp condenser can be found in the cs4953x4/cs497xx system designer?s guide . within each rom id class (3, 4), the breakdown in to two devices per class (CS49530X and cs49531x) is based on the differences between the internal memory size and dsp firmware supported. essentially, the audio processing features of the cs49531x are a supe rset of audio features available in the CS49530X. table 2, ?device and firmware selection guide,? on page 6 provides details of the differences between the two product classes. note: the cs495303/04/14 is available in a 128-pin lqfp package and the cs495313 is available in a 128-pin or 144-pin lqfp package. table 1. cs4953xx related documentation document name description cs4953xx data sheet this document, which contains the hardware specifications for the cs4953xx family cs4953xx hardware user?s manual includes detailed system de sign information for cs4953x3 product family, including typical connection diagrams, boot-procedures, pin descriptions, etc. cs495314/cs4970x4 system designer?s guide a new consolidated documentation set for the cs4953x4 product family that includes: ? detailed system design info rmation incl uding typical connection diagrams, boot procedures, pin descriptions, etc. also describes use of dsp condenser ? tool ? detailed firmware design information including signal processing flow diagrams and control api information an288 - cs4953xx/cs4970x4 firmware user?s manual includes detailed firmware design information including signal processing flow diagrams and control api information
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 5 2.1 migrating fr om cs4953x3 to cs4953x4 ? the recommended way to boot the dsp for normal oper ation is ?master boot?. refer to chapter 1 of the cs4953x4/cs4970x4 system designer?s guide . cs4953x4 supports slave boot mode as well (used for programming the serial flash with the dsp code, through the scp2 port). ? cs4953x4 dsps are only available in 128 pin package. ? the serial flash chip select pin used is pin 14 (g pio0) for master boot. cirrus logic recommends that at least an 8-mb serial flash device be used. refer to cs4953x4/cs4970x4 system designer?s guide for a list of flash types that are currently supported. ? cs4953x4 dsp family supports dsp condenser and dsp manager api for runtime control/host communication. refer to cs4953x4/cs4970x4 system designer?s guide for details. 2.2 licensing licenses are required for all third party audio decoding /processing algorithms, including the application notes. contact your local cirrus sales representative for more information. 3 code overlays the suite of software available for the cs4953xx family consists of an operating system (os) and a library of overlays. the overlays have been divided into thre e main groups called decoder s, matrix-processors, and post-processors. all software components are defined below: ? os/kernel - encompasses all non-audio processing tasks, including loading data from external memory, processing host messages, calling audio-proc essing subroutines, error concealment, etc. ? decoders - any module that initially writes data into the audio i/o buffers, e.g. ac-3 ? , dts, pcm, etc. all the decoding/processing algorithms listed below require delivery of pcm or iec61937-packed, compressed data via i 2 s- or lj-formatted digital audio to the cs4953xx. ? matrix-processors - any module that processes audio i/o buffer pcm data in-place before the post- processors. generally speaking, these modules alter the number of valid channels in the audio i/o buffer through processes like virtualization (n ? 2 channels) or matrix decoding (2 ? n channels). examples are dolby prologic ii, iix, iiz and dts neo:6. ? post-processors - any module that processes audio i/o buffer pcm data in-place after the matrix- processors. examples are bass management, audio manager, tone control, eq, delay, customer- specific effects, dolby headphone 2 and dolby virtual speaker 2, etc. the overlay structure reduces the time required to reconfigure the dsp when a processing change is requested. each overlay can be reloaded independentl y without disturbing the other overlays. for example, when a new decoder is selected, the os, matrix-, and post-processors do not need to be reloaded ? only the new decoder (the same is true for the other overlays). ta b l e 2 below lists the firmware available based on device selection. refer to an288, cs4953xx/cs497xxx firmware user?s manual for the latest listing of application codes and cirrus framework ? modules available.
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 6 table 2. device and firmware selection guide 1 1.this feature list is a snapshot of featur es available as of the public ation date of this revision of the data sheet. more fea tures may now be available. check with your cirrus logic field application engineer (fae) to obtain the latest feature list for the cs495 30x and cs49531x products. device pre- process decode processor (dsp-a) 2 2. additional processing (mpma, mpmb, vpm , ppm) post any of the hd audio decoders may be limited. contact your cirrus logic fae for concurrency matrix. matrix-processor (dsp-a) 2 virtualizer- processor (dsp-b) 2 post-processor (dsp-b) 2 CS49530X 300 m acs n/a stereo pcm multi-channel pcm (2:1 down-sampling option) dolby digital aac mp3 hdcd dolby pro logic ii/iix/iiz 7.1 circle surround ii (stereo in) cirrus original multi- channel surround (effects / reverb processor) down-mix (simultaneous process) dolby headphone dolby virtual speaker srs trusurround xt thx select app (advanced post- processing) ?tone control ?select 2 ?peq (up to 11 bands) ?delay ?7.1 bass manager ?audio manager 1:2 up-sampling cs49531x (superset of CS49530X) 300 m acs lip sync delay same as CS49530X + dts dts-es dts 96/24 same as CS49530X + dts neo:6, dts neural sound (stereo in) same as CS49530X + thx ultra2
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 7 4 hardware functional description 4.1 coyote 32-bit dsp core the cs4953xx is a dual-core dsp with separate x and y data and p code memory spaces. each core is a high-performance, 32-bit, user-progr ammable, fixed-point dsp that is capable of performing two multiply accumulate (mac) operations per clock cycle. each core has eight 72-bit accumulators, four x- and four y-data registers, and 12 index registers. both dsp cores are coupled to a flexible dma engine. the dma engine can move data between peripherals such as the digital audio input (dai) and digital a udio output (dao), external memory, or any dsp core memory, all without the intervention of the dsp. the dma engine offloads data move instructions from the dsp core, leaving more mips available fo r signal processing instructions. cs4953xx functionality is controlled by application codes that are stored in on-board rom or downloaded to the cs4953xx fr om a host mcu or external flash/eeprom. users can choose to use standard audio decoder and post-processor modules which are available from cirrus logic. the cs4953xx is suitable for audio decoder, audio po st-processor, audio encoder, dvd audio/video player, and digital broadcast decoder applications. 4.1.1 dsp memory each dsp core has its own on-chip data and progra m ram and rom and does not require external memory for any of today?s popular audio algorithms includi ng dolby digital surround ex, aac multichannel, dts-es 96/24, and thx ultra2. the memory maps for the dsps are as follows. all memory sizes are composed of 32-bit words. 4.1.2 dma controller the powerful 12-channel dma controlle r can move data between eight on-chip resources. each resource has its own arbiter: x, y, and p ram/ro ms on dsp a; x, y, and p ram/ro ms on dsp b; external memory; and the peripheral bus. modulo and linear addressing mode s are supported, with flexible start address and increment controls. the service inte rval for each dma channel as well as up to six interrupt events, is programmable. table 3. CS49530X dsp memory sizes memory type dsp a dsp b x 16k sram, 16k rom 10k sram, 8k rom y 16k sram, 32k rom 16k sram, 16k rom p 8k sram, 32k rom 8k sram, 24k rom table 4. cs49531x dsp memory sizes memory type dsp a dsp b x 16k sram, 16k rom 10k sram, 8k rom y 24k sram, 32k rom 16k sram, 16k rom p 8k sram, 32k rom 8k sram, 24k rom
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 8 4.2 on-chip dsp peripherals 4.2.1 digital audio input port (dai) the 12-channel (6-line) dai port supports a wide variety of data input formats. the port is capable of accepting pcm or iec61937. up to 32-bit word lengths are supported. the port has two independent slave-only clock domains. each data input can be independently assigned to a clock domain. the sample rate of the input clock doma ins can be determined automatically by the dsp, which off-loads the task of monitoring the s/pdif receiver fr om the host. a time-stamping feature allows the input data to be sample-rate converted via software. 4.2.2 digital audio output port (dao) note: there are two dao ports. each port can output eight channels of up to 32-bit pcm data. the port supports data rates from 32 khz to 192 khz. each port can be configured as an independent clock domain in slave mode, or the ratio of the two clocks can be set to even multiples of each other in master mode. the two ports can also be ganged together into a single clock domain. each port has one serial audio pin that can be configured as a 192 khz s/pdif transmitte r (data with embedded clock on a single line). note: only one s/pdif transmitter pin is available in the 128-pin package. 4.2.3 serial control port 1 & 2 (i 2 c or spi) there are two on-chip serial control ports that are ca pable of operating as master or slave in either i 2 c or spi modes. scp1 defaults to slave operation. it is ded icated for external host-control and supports an external clock up to 50 mhz in spi mode. it is present in both the 144- and 128-pin packages. this high clock speed enables very fast code download, control or data deliver y. scp2 defaults to master mode and is dedicated for booting from external serial flash memory or for a udio sub-system control. scp2 does not include the scp2_bsy# pin in the 128-pin package. 4.2.4 parallel control port the cs4953xx parallel port supports both motorola ? and intel ? interfaces. it can be used for both control and data delivery. the parallel port pins ar e multiplexed with serial control port 2 and are available in the 144-pin package. 4.2.5 external memory interface the external memory interface controller supports up to 128 mb of sdram, using a 16-bit data bus. 4.2.6 general purpose input/output (gpio) many of the cs4953xx peripheral pins are multiplexed with gpio. each gpio can be configured as an output, an input, or an input with in terrupt. each input-pin in terrupt can be conf igured as rising edge, falling edge, active-low, or active-high. 4.2.7 phase-locked loop (pll)-based clock generator the low-jitter pll generates in teger or fractional multiples of a reference frequency which are used to clock the dsp core and peripherals. through a second pll divi der chain, a dependent clock domain can be output on the dao port for driving audio converters. the cs4953xx defaults to running from the external reference frequency and can be switched to use the pll output after overlays have been loaded and configured, either through master boot fr om an external serial flash or through host contro l. a built-in crystal oscillator circuit with a buffered output is provided. the buffered output frequency ratio is selectable between 1:1 (default) or 2:1. 4.3 dsp i/o description 4.3.1 multiplexed pins many of the cs4953xx pins are multi-functional . for details on pin functionality, refer to the cs4953xx hardware user?s manual .
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 9 4.3.2 termination requirements open-drain pins on the cs4953xx must be pulled high for proper operation. refer to the cs4953xx hardware user?s manual to identify which pins are open-drain and what value of pull-up resistor is required for proper operation. mode select pins on the cs4953xx are used to select t he boot mode upon the rising edge of reset. a detailed explanation of termination requirements for each co mmunication mode select pin can be found in the cs4953xx hardware user?s manual . 4.3.3 pads the cs4953xx i/o operates from the 3.3 v supply and is 5 v tolerant. 4.4 applicati on code security the external program code may be encrypted by the prog rammer to protect any intellectual property it may contain. a secret, customer-specific key is used to encrypt the program code that is to be stored external to the device. 5 characteristics and specifications note: all data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. all data sheet typical parameters ar e measured under the following conditions: t = 25 c, c l = 20 pf, vdd = vdda = 1.8 v, vddio = 3.3 v, gndd = gndio = gnda = 0 v. 5.1 absolute maximum ratings (gndd = gndio = gnda = 0 v; all voltages with respect to 0 v) caution: operation at or beyond these limits may result in permanen t damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min max unit dc power supplies: core supply pll supply i/o supply |vdda ? vddio| vdd vdda vddio ?0.3 ?0.3 ?0.3 - 2.0 3.6 3.6 0.3 v v v v input pin current, any pin except supplies i in ?+/- 10ma input voltage on pll_ref_res v filt -0.3 3.6 v input voltage on i/o pins v inio -0.3 5.0 v storage temperature t stg ?65 150 c
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 10 5.2 recommended op erating conditions (gndd = gndio = gnda = 0 v; all voltages with respect to 0 v) note: it is recommended that the 3.3 v io supply come up ah ead of or simultaneously with the 1.8 v core supply. 5.3 digital dc characteristics (measurements performed under static conditions.) 5.4 power supply characteristics (measurements performed under operating conditions) parameter symbol min typ max unit dc power supplies: core supply pll supply i/o supply |vdda ? vddio| vdd vdda vddio 1.71 3.13 3.13 1.8 3.3 3.3 0 1.89 3.46 3.46 v v v v ambient operating temperature commercial grade (cqz/cvz) automotive grade (dqz/dvz) t a 0 - 40 +25 +25 + 70 + 85 c commercial automotive t j 0 -40 ?+125 +125 oc parameter symbol min typ max unit high-level input voltage v ih 2.0 ? ? v low-level input voltage, except xti v il ??0.8 v low-level input voltage, xti v ilxti ??0.6 v input hysteresis v hys ?0.4 ? v high-level output voltage (i o = -4ma), except xti, sdram pins v oh vddio * 0.9 ? ? v low-level output voltage (i o = 4ma), except xti, sdram pins v ol ??vddio * 0.1v sdram high-level output voltage (i o = -8ma) v oh vddio * 0.9 ? ? v sdram low-level output voltage (i o = 8ma) v ol ??vddio * 0.1v input leakage current (all digital pins with internal pull-up resistors disabled) i in ?? 5 a input leakage current (all digital pins with internal pull-up resistors enabled, and xti) i in-pu ?? 70 a parameter min typ max unit power supply current: core and i/o operating: vdd 1 pll operating: vdda with external memory and most ports operating: vddio 1. dependent on application firmware and dsp clock speed. ? ? ? 350 3.5 120 ? ? ? ma ma ma
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 11 5.5 thermal data (144-pin lqfp) 5.6 thermal data (128-pin lqfp) notes: 1. two-layer board is specified as a 76 mm x 114 mm, 1.6 mm thick fr-4 material with 1-oz copper covering 20 % of the top & bottom layers. 2. four-layer board is specified as a 76 mm x 114 mm, 1. 6 mm thick fr-4 material with 1-ounce copper covering 20 % of the top & bottom layers and 0.5-ounce copper covering 90 % of the internal power plane and ground plane layers. 3. to calculate the die temperature for a given power dissipation j = ambient temperature + [ (power dissipation in watts) * ja ] 4. to calculate the case temperature for a given power dissipation c = j - [ (power dissipation in watts) * jt ] parameter symbol min typ max unit thermal resistance (junction to ambient) two-layer board 1 four-layer board 2 ja ? ? 48 40 ? ? c / watt thermal resistance (junction to top of package) two-layer board 1 four-layer board 2 jt ? ? .39 .33 ? ? c / watt parameter symbol min typ max unit thermal resistance (junction to ambient) two-layer board 1 four-layer board 2 ja ? ? 53 44 ? ? c / watt thermal resistance (junction to top of package) two-layer board 1 four-layer board 2 jt ? ? .45 .39 ? ? c / watt
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 12 5.7 switching ch aracteristics?reset figure 1. reset timing 5.8 switching char acteristics ? xti figure 2. xti timing parameter symbol min max unit reset minimum pulse width low t rstl 1? s all bidirectional pins high-z after reset low t rst2z /m 100 ns configuration pins setup before reset high t rstsu 50 ? ns configuratio n pins hold after reset high t rsthld 20 ? ns parameter symbol min max unit external crystal operating frequency 1 1. part characterized with the following crystal frequency values: 12.288 and 24.576 f xtal 12.288 24.576 mhz xti period t clki 41 81.4 ns xti high time t clkih 16.4 /m ns xti low time t clkil 16.4 ? ns external crystal load capacitance (parallel resonant) 2 2. c l refers to the total load capacitance as specified by the crystal manufacturer. crystals which require a c l outside this range should be avoided. the crystal oscillator circuit design should follow the crystal manufacturer?s recommendation for load capacitor selection. c l 10 18 pf external crystal equivalent series resistance esr ? 50 reset# t rst2z t rstl t rstsu t rsthld hs[3:0] all bidirectional pins t clkih t clkil t clki xti
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 13 5.9 switching characteris tics ? internal clock parameter symbol min max unit internal dclk frequency 1 1. after initial power-on reset, f dclk = f xtal . after initial kick-start commands, the pll is locked to max f dclk and remains locked until the next power-on reset. f dclk ?130mhz CS49530X-cvz cs49531x-cqz cs49531x-cvz CS49530X-dvz cs49531x-dvz ?f xtal f xtal f xtal f xtal f xtal 150 150 150 131 131 ? internal dclk period 1 dclkp ? 7.7 ns CS49530X-cvz cs49531x-cqz cs49531x-cvz CS49530X-dvz cs49531x-dvz ?6.7 6.7 6.7 7.63 7.63 1/f xtal 1/f xtal 1/f xtal 1/f xtal 1/f xtal ?
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 14 5.10 switching character istics ? serial control port - spi slave mode parameter symbol min typical max units scp_clk frequency 1,2 1. the specification f spisck indicates the maximum speed of the hardware. the system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware applic ation. flow control using the scp_bsy pin should be implemented to prevent overflow of the input data buffer. at boot the maximum speed is f xtal /3. 2. when scp1 is in spi slave mode, very slow rise and fall times of the scp_clk edges may make the edges of the scp_clk more susceptible to noise, resulting in non-smoot h edges. any glitch at the threshold levels of the scp port input signals could result in abnormal operation of the port. in systems that have noise coupling onto scp_clk, sl ow rise and fall times may cause host communication problems. increasing rise time makes host communication more reliable. f spisck ?? 25mhz scp_cs falling to scp_clk rising 2 t spicss 24 ? ? ns scp_clk low time 2 t spickl 20 ? ? ns scp_clk high time 2 t spickh 20 ? ? ns setup time scp_mosi input t spidsu 5? ?ns hold time sc p_mosi input t spidh 5? ?ns scp_clk low to scp_ miso output valid 2 t spidov ?? 11ns scp_clk fallin g to scp_irq rising 2 t spiirqh ? ? 20 ns scp_cs rising to scp_irq falling 2 t spiirql 0? ?ns scp_clk low to scp_cs rising 2 t spicsh 24 ? ? ns scp_cs rising to scp_miso output high-z t spicsdz ?20 ?ns scp_clk rising to scp_bsy falling 2 t spicbsyl ?3 * dclkp+20 ? ns
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 15 figure 3. serial control po rt - spi slave mode timing scp_bsy scp_cs scp_clk scp_mosi scp_miso scp_irq 0 12670 56 7 t spicss t spickl t spickh t spidsu t spidh t spidov a6 a5 a0 r/w msb lsb msb lsb t spicsh t spibsyl t spiirql t spiirqh f spisck t spicsdz
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 16 5.11 switching character istics ? serial control port - spi master mode figure 4. serial control port - spi master mode timing parameter symbol min typical max units scp_clk frequency 1,2 1. the specification f spisck indicates the maximum speed of the hardware. the system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. 2. see section 5.8 . f spisck ??f xtal /2 mhz scp_cs falling to scp_clk rising 3 3. scp_clk period refers to the period of scp_clk as being used in a given application. it does not refer to a tested parameter t spicss ? 11*dclkp + (scp_clk period)/2 ?ns scp_clk low time t spickl 16.9 ? ? ns scp_clk high time t spickh 16.9 ? ? ns setup time scp_miso input t spidsu 11 ? ? ns hold time sc p_miso input t spidh 5? ?ns scp_clk low to scp_ mosi output valid t spidov ?? 11ns scp_clk low to scp_cs falling t spicsl 7? ?ns scp_clk low to scp_cs rising t spicsh ? 11*dclkp + (scp_clk period)/2 ?ns bus free time between active scp_cs t spicsx ?3*dclkp ?ns scp_clk falling to sc p_mosi output high-z t spidz ? ? 20 ns ee_cs scp_clk scp_miso scp_mosi 012670567 t spicss t spickl t spickh t spidsu t spidh t spidov a6 a5 a0 r/w msb lsb msb lsb t spicsh t spicsx f spisck t spidz t spicsl
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 17 5.12 switching char acteristics ? serial control port - i 2 c slave mode figure 5. serial control port - i 2 c slave mode timing parameter symbol min typical max units scp_clk frequency 1 1. the specification f iicck indicates the maximum speed of the hardware. the system desi gner should be aware that the actual maximum speed of the communication port may be limited by the firmware application. flow control using the scp_bsy pin should be implemented to prevent overflow of the input data buffer. f iicck ? ? 400 khz scp_clk low time t iicckl 1.25 ? ? s scp_clk high time t iicckh 1.25 ? ? s scp_sck rising to scp_sda risi ng or falling for start or stop condition t iicckcmd 1.25 ? ? s start condition to scp_clk falling t iicstscl 1.25 ? ? s scp_clk falling to stop condition t iicstp 2.5 ? ? s bus free time between stop and start conditions t iicbft 3? ?s setup time scp_sda input valid to scp_clk rising t iicsu 100 ? ? ns hold time scp_sda input after scp_clk falling 2 2. this parameter is measured from the vil level at the falling edge of the clock. t iich 0? ?ns scp_clk low to scp_sda out valid t iicdov ?? 18 ns scp_clk fallin g to scp_irq rising t iicirqh ??3 * dclkp + 40 ns nak condition to scp_irq low t iicirql ?3 * dclkp + 20 ? ns scp_clk rising to scb_bsy low t iicbsyl ?3 * dclkp + 20 ? ns scp_bsy scp_clk scp_sda scp_irq 01 67801 7 t iicckl t iicckh t iicsu t iich a6 a0 r/w ack lsb t iicirqh t iicirql 8 ack msb t iicstp 6 t iiccbsyl t iicdov t iicbft t iicstscl t iicckcmd f iicck t iicckcmd t iicf t iicr
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 18 5.13 switching char acteristics ? serial control port - i 2 c master mode figure 6. serial control port - i 2 c master mode timing parameter symbol min max units scp_clk frequency 1 1. the specification f iicck indicates the maximum speed of the hardware. the system desi gner should be aware that the actual maximum speed of the communication port may be limited by the firmware application. f iicck ? 400 khz scp_clk low time t iicckl 1.25 ? s scp_clk high time t iicckh 1.25 ? s scp_sck rising to scp_ sda rising or falling for start or stop condition t iicckcmd 1.25 ? s start condition to scp_clk falling t iicstscl 1.25 ? s scp_clk falling to stop condition t iicstp 2.5 ? s bus free time between stop and start conditions t iicbft 3?s setup time scp_sda input valid to scp_clk rising t iicsu 100 ? ns hold time scp_sda input after scp_clk falling 2 2. this parameter is measured from the vil level at the falling edge of the clock. t iich 0?ns scp_clk low to scp_sda out valid t iicdov ?36ns scp_clk scp_sda 01 67801 7 t iicckl t iicckh t iicsu t iich a6 a0 r/w ack lsb 8 ack msb t iicstp 6 t iicdov t iicbft t iicstscl t iicckcmd f iicck t iicckcmd t iicf t iicr
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 19 5.14 switching characteris tics ? parallel control port - intel slave mode parameter symbol m in typical max unit address setup before pcp_cs and pcp_rd low or pcp_cs and pcp_wr low t ias 5??ns address hold time after pcp_cs and pcp_rd low or pcp_cs and pcp_wr high t iah 5??ns read delay between pcp_rd then pcp_cs low or pcp_cs then pcp_rd low t icdr 0??ns data valid after pcp_cs and pcp_rd low t idd ? ? 18 ns pcp_cs and pcp_rd low for read t irpw 24 ? ? ns data hold time after pcp_cs or pcp_rd high t idhr 8??ns data high-z after pcp_cs or pcp_rd high t idis ? ? 18 ns pcp_cs or pcp_rd high to pcp_cs and pcp_rd low for next read 1 1. the system designer should be aware t hat the actual maximum speed of the communication port may be limited by the firmware application. hardware handshaking on the pcp_bsy pin/bit should be observed to prevent overflowing the input data buffer. an288 cs4953xx /cs497xxx firm ware user?s manual should be consulted for the firmware speed limitations. t ird 30 ? ? ns pcp_cs or pcp_rd high to pcp_cs and pcp_wr low for next write 1 t irdtw 30 ? ? ns pcp_rd rising to pcp_irq rising t irdirqhl ? ? 12 ns write delay between pcp_wr then pcp_cs low or pcp_cs then pcp_wr low t icdw 0??ns data setup before pcp_cs or pcp_wr high t idsu 8??ns pcp_cs and pcp_wr low for write t iwpw 24 ? ? ns data hold after pcp_cs or pcp_wr high t idhw 8??ns pcp_cs or pcp_wr high to pcp_cs and pcp_rd low for next read 1 t iwtrd 30 ? ? ns pcp_cs or pcp_wr high to pcp_cs and pcp_wr low for next write 1 t iwd 30 ? ? ns pcp_wr rising to pcp_bsy falling t iwrbsyl ?2*dclkp + 20? ns
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 20 figure 7. parallel control port - intel slave mode read cycle figure 8. parallel control port - intel slave mode write cycle pcp_a[3:0] pcp_d[7:0] t ias t icdr t iah t idd t irpw t idhr t idis t ird t irdtw pcp_cs pcp_wr pcp_rd pcp_irq t irdirqh lsp msp t ias t icdw t iah t iwpw t idhw t iw d t iwtrd t idsu t iwrbsyl pcp_d[7:0] pcp_cs pcp_wr pcp_rd pcp_a[3:0] pcp_bsy lsp msp
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 21 5.15 switching characteris tics ? parallel control po rt - motorola slave mode parameter symbol min typical max unit address setup before pcp_cs and pcp_ds low t mas 5??ns address hold time after pcp_cs and pcp_ds low t mah 5??ns read delay between pcp_ds then pcp_cs low or pcp_cs then pcp_ds# low t mcdr 0??ns data valid after pcp_cs and pcp_ds low with pcp_r/w high t mdd ? ? 19 ns pcp_cs and pcp_ds low for read t mrpw 24 ? ? ns data hold time after pcp_cs or pcp_ds high after read t mdhr 8??ns data high-z after pcp_cs or pcp_ds high after read t mdis ? ? 18 ns pcp_cs or pcp_ds high to pcp_cs and pcp_ds low for next read 1 1. the system designer should be aware that the actual maximum speed of th e communication port may be limited by the firmware application. hardware handshaking on the pcp_bsy pin/bit should be observed to prevent overflowing the input data buffer. an288 cs4953xx/cs497xxx firmware user?s manual should be consulted for the firmware speed limitations. t mrd 30 ? ? ns pcp_cs or pcp_ds high to pcp_cs and pcp_ds low for next write 1 t mrdtw 30 ? ? ns pcp_rw rising to pcp_irq falling t mrwirqh ? ? 12 ns write delay between pcp_ds then pcp_cs low or pcp_cs then pcp_ds low t mcdw 0??ns data setup before pcp_cs or pcp_ds high t mdsu 8??ns pcp_cs and pcp_ds low for write t mwpw 24 ? ? ns pcp_r/w setup before pcp_cs and pcp_ds low t mrwsu 24 ? ? ns pcp_r/w hold time after pcp_cs or pcp_ds high t mrwhld 8??ns data hold after pcp_cs or pcp_ds high t mdhw 8??ns pcp_cs or pcp_ds high to pcp_cs and pcp_ds low with pcp_r/w high for next read 1 t mwtrd 30 ? ? ns pcp_cs or pcp_ds high to pcp_cs and pcp_ds low for next write 1 t mwd 30 ? ? ns pcp_rw rising to pcp_bsy falling t mrwbsyl ? 2*dclkp + 20 ? ns
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 22 figure 9. parallel control port - mo torola slave mode read cycle timing figure 10. parallel control port - mo torola slave mode write cycle timing t mas t mcdr t mah t mdd t mrpw t mdhr t mdis t mrd t mrdtw t mrwsu t mrwhld pcp_a[3:0] pcp_ad[7:0] pcp_cs pcp_wr pcp_ds pcp_irq t mrwirqh lsp msp t mas t mdsu t mdhw t mwd t mwtrd t mwpw t mcdw t mrwsu t mrwhld mah t pcp_a[3:0] pcp_ad[7:0] pcp_cs pcp_wr pcp_ds pcp_irq t mrwirql lsp msp
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 23 5.16 switching char acteristics ? digital audio slave input port note: in these diagrams, falling edge is the inactive edge of dai_sclk. figure 11. digital audio input (dai) port timing diagram figure 12. dai slave timing diagram parameter symbol min max unit dai_sclk period t daiclkp 40 ? ns dai_sclk duty cycle ?4555% dai_lrclk transition from dai_sclk active edge t daisstlr 10 ? ns dai_sclk active edge from dai_lrclk transition t daislrts 10 ? ns setup time dai_datan t daidsu 10 ? ns hold time dai_datan t daidh 5?ns dai_sclk dai_datan t daidh t daidsu dai_sclk dai_lrclk dain_datan t daislrts t daiclkp dai_sclk dai_lrclk t daisstlr t daiclkp dain_datan
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 24 5.17 switching char acteristics ? digital audio output port figure 13. digital audio port output timing master mode parameter symbol min max unit dao_mclk period t daomclk 40 ? ns dao_mclk duty cycle ?45 55% dao_sclk period for master or slave mode 1 1. master mode timing specifications ar e characterized, not production tested. t daosclk 40 ? ns dao_sclk duty cycle for master or slave mode 1 ?40 60% master mode (output a1 mode) 1,2 2. master mode is defined as the cs4 953xx driving both dao_sclk and dao_lr clk. when mclk is an input, it is divided to produce dao_sclk, dao_lrclk. dao_sclk delay from dao_mclk rising edge, dao_mclk as an input t daomsck ?19ns dao_sclk delay from dao_lrclk transition 3 t daomlrts ?8ns dao_lrclk delay from dao_sclk transition 3 3. this timing parameter is defined from the non-active edge of dao_sclk. the active edge of dao_sclk is the point at which the data is valid. t daomstlr ?8ns dao1_data[3:0], dao2_data[1:0] delay from dao_sclk transition 3 t daomdv ?10ns slave mode (output a0 mode) 4 4. slave mode is defined as dao_sclk, dao_lrclk driven by an external source. dao_sclk active edge to dao_lrclk transition t daosstlr 10 ? ns dao_lrclk transition to dao_sclk active edge t daoslrts 10 ? ns dao_dx delay from dao_sclk inactive edge t daosdv ?12.5ns dao_mclk dao_sclk dao_lrclk daon_datan t daomlclk t daomsck t daomdv t daomlrts dao_mclk dao_sclk dao_lrclk daon_datan t daomclk t daomsck t daomstlr note: in these diagrams, falling edge is the inactive edge of dao_sclk
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 25 figure 14. digital audio output timing, slave mode 5.18 switching character istics ? sdram interface refer to figure 15 through figure 18 . (sd_clkout = sd_clkin) parameter symbol min typical max unit sd_clkin high time t sdclkh 2.3 ? ? ns sd_clkin low time t sdclkl 2.3 ? ? ns sd_clkout rise/fall time t sdclkrf ??1ns sd_clkout frequency ??150?mhz sd_clkout duty cycle ?45 ?55% sd_clkout rising edge to signal valid t sdcmdv ??3.8ns signal hold from sd_clkout rising edge t sdcmdh ?1.1?ns sd_clkout rising edge to sd_dqmn valid t sddqv ?3.8?ns sd_dqmn hold from sd_clkout rising edge t sddqh 1.38 ? ? ns sd_data valid setup to sd_clkin rising edge t sddsu 1.3 ? ? ns sd_data valid hold to sd_clkin rising edge t sddh 2.1 ? ? ns sd_clkout rising edge to addrn valid t sdav ?3.8?ns dao_sclk dao_lrclk dao_dx t daoslrts t daosclk dao_sclk dao_lrclk t daosstlr t daosdv t daosclk dao_dx
ds705f2 26 cs4953xx data sheet 32-bit audio decoder dsp family figure 15. external memory interface - sdram burst read cycle figure 16. external memory inte rface - sdram burst write cycle sd_clkout sd_cs sd_ras sd_cas sd_we sd_dqmn sd_an sd_dn t sddsu t sdclkrf t sdcmdv t sdav t sddqv t sdcmdh t sddh t sddqh cas=2 lsp0 msp0 lsp3 msp3 sd_clkin t sdclkl t sdclkh 00 11 lsp1 msp1 lsp2 msp2 sd_clkout sd_cs sd_ras sd_cas sd_we t sdcmdv t sdcmdh sd_dn lsp 0 msp0 lsp1 msp1 lsp2 msp2 lsp3 msp3 sd_an sd_dqmn t sddqh 00 11 t sddqv t sdav
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 27 figure 17. external memory inte rface - sdram auto refresh cycle figure 18. external memo ry interface - sdram load mode register cycle sd_clkout sd_cs sd_ras sd_cas sd_we sd_dqmn sd_an sd_dn t sdcmdv t sdcmdh t sdcmdv sd_clkout sd_cs sd_ras sd_cas sd_we sd_dqmn sd_an sd_dn opcode t sdcmdv t sdcmdh
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 28 6 ordering information the cs4953xx family part number is described as follows: cs495nni-xyz where nn - product number variant i - rom id number x - product grade y - package type z - lead (pb) free . table 5. ordering information part no. status grade temp. range package status cs495303-cvz nrnd commercial 0 to +70 c 128-pin lqfp ? cs495303-cvzr 1 1. r = tape and reel nrnd ? cs495303-cqz eol 144-pin lqfp ? cs495304-cvz eol 128-pin lqfp ? cs495304-cvzr 1 eol ? cs495304-dvz eol automotive -40 to +85 c 128-pin lqfp ? cs495304-dvzr 1 eol ? cs495313-cqz eol commercial 0 to +70 c 144-pin lqfp ? cs495313-cqzr 1 eol ? cs495313-cvz nrnd commercial 0 to +70 c 128-pin lqfp ? cs495313-cvzr 1 nrnd ? cs495314-cvz 2 2. recommended for new designs. see section 2 for details about cirrus logic design recommendations. active commercial 0 to +70 c 128-pin lqfp ? cs495314-cvzr 1,2 active ? cs495314-cqz eol 144-pin lqfp ? cs495314-dvz active 128-pin lqfp ? cs495314-dvzr 1 note 3 3. contact the factory for availability of the -d (automotive grade) package automotive -40 to +85 c 128-pin lqfp ?
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 29 7 environmental, manufacturing, and handling information * msl (moisture sensitivity level) as specified by ip c/jedec j-std-020. table 6. environmental, manufacturing, and handling information model number peak reflow temp msl rating* max floor life cs495303-cvz 260 c 3 7 days cs495303-cvzr cs495304-cvz cs495304-cvzr cs495304-dvz cs495304-dvzr cs495313-cqz cs495313-cqzr cs495313-cvz cs495313-cvzr cs495314-cvz cs495314-cvzr cs495314-dvz cs495314-dvzr
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 30 8 device pinout diagrams 8.1 128-pin lqfp pinout diagrams (cs495303/cs495313) the cs495303/cs495313 dsp with a 128-pin package is not recommended for new designs. see section 2 for details about this cirrus logic recommendation. figure 19. 128-pin lqfp pin-out drawing (cs495303/cs495313) gpio2 gpio1 gpio0 xto vdd7 gnd7 vddio7 xti gndio7 gnda pll_ref_res vdda (3.3v) vdd8 gnd8 gpio13, dai1_data2, tm2, dsd2 gpio14, dai1_data3, tm3, dsd3 dai1_data0, tm0, dsd0 gpio12, dai1_data1, tm1, dsd1 gpio6, pcp_cs, scp2_cs gpio38, pcp_wr, pcp_ds, scp2_clk vdd6 gnd6 gpio10, pcp_a2, pcp_a10, scp2_mosi gpio8, pcp_irq, scp2_irq gpio37, scp1_bsy, pcp_bsy vddio6 gpio11, pcp_a3, pcp_as, scp2_miso, scp2_sda gndio6 gpoi 9, scp1_irq gpio34, scp1_miso, scp1_sda gpio33, scp1_mosi gpio35, scp1_clk vdd5 vddio5 gnd5 gndio5 sd_cas sd_ras sd_a3, ext_a3 sd_a2, ext_a2 sd_a1, ext_a1 sd_a0, ext_a0 sd_a10, ext_a10 sd_a11, ext_a11 vdd4 gnd4 sd_cs sd_a4, ext_a4 sd_a5, ext_a5 sd_a6, ext_a6 sd_a7, ext_a7 sd_a8, ext_a8 sd_clken sd_a9, ext_a9 vddio4 gndio4 sd_clkout sd_clkin sd_d10, ext_d10 sd_d11, ext_d11 sd_d12, ext_d12 vdd3 gnd3 sd_d13, ext_d13 sd_d14, ext_d14 sd_d15, ext_d15 sd_dqm1 sd_d7, ext_d7 sd_d6, ext_d6 vddio3 gndio3 sd_d5, ext_d5 sd_dqm0 sd_d4, ext_d4 sd_d3, ext_d3 sd_d2, ext_d2 gpio17, dao1_data3, xmta gpio15, dao1_data1, hs1 dao1_data0, hs0 dao1_l rcl k dai1_lrclk, dsd4 dao_mclk gpio20, dao2_data2, ee_cs dai1_sclk, dsd_clk vdd1 gnd1 dao1_sclk gpio16, dao1_data2, hs2 gp io23, dao2_lrclk re set vddio1 gpio22, dao2_sclk gndio1 gpio18, dao2_data0, hs3 gpio19, dao2_data1, hs4 vdd2 gnd2 gpio26, dao2_data3, xmtb vddio2 gndio2 sd_we sd_d0, ext_d0 sd_d1, ext_d1 sd_d8, ext_d8 sd_d9, ext_d9 sd_a12, ext_a12 sd_ba1, ext_a14 sd_ba0, ext_a13 gpio7, scp1_cs, iowait vddio8 gndio8 ext_a15 ext_a16 ext_a17 ext_a18 ext_a19 ext_cs1 ext_oe ext_we gpio3, ddac test dbda dbck xtal_out gpio43, bdi_clk, dai2_sclk gpio42, bdi_req, dai2_lrclk, pcp_irq, pcp_bsy bdi_data, dai2_data, dsd5 ext_cs2 10 15 20 25 30 5 35 1 125 120 115 110 105 95 90 85 80 75 70 65 100 40 45 50 55 60 128-pin lqfp (cs495303/cs49513)
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 31 8.2 128-pin lqfp pinout diagrams (cs495304/cs495314) the cs495304/cs495314 dsp with a 128-pin package is recommended for new designs. see section 2 for details about this cirrus logic recommendation. figure 20. 128-pin lqfp pin-out drawing (cs495304/cs495314) gpio2 gpio1 gpio0, uart_clk, ee_cs xto vdd7 gnd7 vddio7 xti gndio7 gnda pll_ref_res vdda (3.3v) vdd8 gnd8 gpio13, dai1_data2, tm2, dsd2 gpio14, dai1_data3, tm3, dsd3 dai1_data0, tm0, dsd0 gpio12, dai1_data1, tm1, dsd1 gpio6, pcp_cs, scp2_cs gpio38, pcp_wr, pcp_ds, scp2_clk vdd6 gnd6 gpio10, pcp_a2, pcp_a10, scp2_mosi gpio8, pcp_irq, scp2_irq gpio37, scp1_bsy, pcp_bsy vddio6 gpio11, pcp_a3, pcp_as, scp2_miso, scp2_sda gndio6 gpoi 9, scp1_irq gpio34, scp1_miso, scp1_sda gpio33, scp1_mosi gpio35, scp1_clk vdd5 vddio5 gnd5 gndio5 sd_cas sd_ras sd_a3, ext_a3 sd_a2, ext_a2 sd_a1, ext_a1 sd_a0, ext_a0 sd_a10, ext_a10 sd_a11, ext_a11 vdd4 gnd4 sd_cs sd_a4, ext_a4 sd_a5, ext_a5 sd_a6, ext_a6 sd_a7, ext_a7 sd_a8, ext_a8 sd_clken sd_a9, ext_a9 vddio4 gndio4 sd_clkout sd_clkin sd_d10, ext_d10 sd_d11, ext_d11 sd_d12, ext_d12 vdd3 gnd3 sd_d13, ext_d13 sd_d14, ext_d14 sd_d15, ext_d15 sd_dqm1 sd_d7, ext_d7 sd_d6, ext_d6 vddio3 gndio3 sd_d5, ext_d5 sd_dqm0 sd_d4, ext_d4 sd_d3, ext_d3 sd_d2, ext_d2 gpio17, dao1_data3, xmta gpio15, dao1_data1, hs1 dao1_dat a0, hs0 da o1_l rcl k dai1_lrclk, dsd4 dao_mclk gpio20, dao2_data2 dai1_sclk, dsd_clk vdd1 gnd1 dao1_scl k gpio16, dao1_data2, hs2 gpio23, dao2_lrclk reset vddio1 gpio22, dao2_sclk gndio1 gpio18, dao2_data0, hs3 gpio19, dao2_data1, hs4 vdd2 gnd2 gpio26, dao2_data3, xmtb vddio2 gndio2 sd_we sd_d0, ext_d0 sd_d1, ext_d1 sd_d8, ext_d8 sd_d9, ext_d9 sd_a12, ext_a12 sd_ba1, ext_a14 sd_ba0, ext_a13 gpio7, scp1_cs, iowait vddio8 gndio8 ext_a15 ext_a16 ext_a17 ext_a18 ext_a19 ext_cs1 ext_oe ext_we gpio3, ddac test dbda dbck xtal_out gpio43, bdi_clk, dai2_sclk gpio42, bdi_req , dai2_lrclk, pcp_irq, pcp_ibsy bdi_data, dai2_data, dsd5 ext_cs2 10 15 20 25 30 5 35 1 125 120 115 110 105 95 90 85 80 75 70 65 100 40 45 50 55 60 128-pin lqfp (cs495304/cs495314)
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 32 8.3 144-pin lqfp pinout diagrams (cs495313) the cs495313 dsp with a 144-pin package is not recommended for new designs. see section 2 for details about this cirrus logic recommendation. figure 21. 144-pin lqfp pin-out drawing (cs495313) gpio1, pcp_ad1, pcp_d1 gpio0, pcp_ad0, pcp_d0 gpio25 gpio24 gpio31 xto vdd7 gnd7 vddio7 xti gndio7 gnda nc pll_ref_res vdda (3.3v) vdd8 gnd8 gpio13, dai1_data2, tm2, dsd2 gpio14, dai1_data3, tm3, dsd3 dai1_data0, tm0, dsd0 gpio12, dai1_data1, tm1, dsd1 gpio2, pcp_ad2, pcp_d2 gpio3, pcp_ad3, pcp_d3 gpio4, pcp_ad4, pcp_d4 gpio5, pcp_ad5, pcp_d5 gpio6, pcp_ad6, pcp_d6 gpio39, pcp_cs, scp2_cs gpio7, pcp_ad7, pcp_d7 gpio9, pcp_a1, pcp_a9 gpio38, pcp_wr, pcp_ds, scp2_clk vdd6 gpio40, pcp_rd, pcp_rw gnd6 gpio10, pcp_a2. pcp_a10, s cp2_mosi gpio41, pcp_irq, scp2_irq gpio37, scp1_bsy, pcp_bsy vddio6 gpio11, pcp_a3, pcp_as, scp2_mis o, scp2_sda gndio6 gpoi36, scp1_irq gpio34, scp1_miso, scp1_sda gpio33, scp1_mosi gpio35, scp1_clk vdd5 vddio5 gnd5 gndio5 sd_cas sd_ras sd_a3, ext_a3 sd_a2, ext_a2 sd_a1, ext_a1 sd_a0, ext_a0 sd_a10, ext_a10 sd_a11, ext_a11 vdd4 gnd4 sd_cs sd_a4, ext_a4 sd_a5, ext_a5 sd_a6, ext_a6 sd_a7, ext_a7 sd_a8, ext_a8 sd_clken sd_a9, ext_a9 vddio4 gndio4 sd_clkout sd_clkin sd_d10, ext_d10 sd_d11, ext_d11 sd_d12, ext_d12 vdd3 gnd3 sd_d13, ext_d13 sd_d14, ext_d14 sd_d15, ext_d15 sd_dqm1 sd_d7, ext_d7 sd_d6, ext_d6 vddio3 gndio3 sd_d5, ext_d5 sd_dqm0 sd_d4, ext_d4 sd_d3, ext_d3 sd_d2, ext_d2 gpio26 gpio17, dao1_data3, xmta gpio15, dao1_data1, hs1 da o1_dat a0, hs0 dao1_lrclk dai1_lrclk, dsd4 dao_mclk gpio20, dao2_data2, ee_cs dai1_sclk, dsd_clk vdd1 gnd1 dao1_sclk gpio16, dao1_data2, hs2 gpio23, dao2_lrclk reset vddio1 gpio22, dao2_sclk gndio1 gpio18, dao2_data0, hs3 gpio19, dao2_data1, hs4 vdd2 gnd2 gpio21, dao2_data3, xmtb vddio2 gndio2 sd_we sd_d0, ext_d0 sd_d1, ext_d1 sd_d8, ext_d8 sd_d9, ext_d9 sd_a12, ext_a12 sd_ba1, ext_a14 sd_ba0, ext_a13 gpio32, scp1_cs, iowait vddio8 gndio8 ext_a15 ext_a16 ext_a17 ext_a18 ext_a19 ext_cs1 gpio8, pcp_a0, pcp_a8 ext_cs2 ext_oe ext_we gpio27 gpio28, ddac gpio29, xmta_in gpio30, xmtb_in test dbda dbck xtal_out gpio43, bdi_clk, dai2_sclk pio42, bdi_req , dai2_lrclk, pcp_irq, pcp_bsy bdi_data, dai2_data, dsd5 113 116 119 122 126 129 130 133 136 139 109 110 115 120 125 135 140 144 1 5 9 10 13 18 21 24 27 33 36 15 25 30 35 101 98 94 91 86 83 76 73 75 80 85 90 95 100 105 108 69 66 63 60 57 54 47 44 37 40 45 50 55 65 70 72 144-pin lqfp (cs495313)
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 33 9 package mechanical drawings 9.1 128-pin lqfp package drawing figure 22. 128-pin lqfp package drawing table 7. 128-pin lqfp package characteristics dim millimeters inches min nom max min nom max a ? ? 1.60 ? ? .063? a1 0.05 ? 0.15 .002? ? .006? b 0.17 0.22 0.27 .007? .009? .011? d 22.00 bsc .866? d1 20.00 bsc .787? e 16.00 bsc .630? e1 14.00 bsc .551? e 0.50 bsc .020? q 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 .018? .024? .030? l1 1.00 ref .039? ref tolerances of form and position ddd 0.08 .003? d1 d e1 e 1 e l b a1 a
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 34 9.2 144-pin lqfp package drawing figure 23. 144-pin lqfp package drawing table 8. 144-pin lqfp package characteristics dim millimeters inches min nom max min nom max a ? ? 1.60 ? ? .063? a1 0.05 ? 0.15 .002? ? .006? b 0.17 0.22 0.27 .007? .009? .011? d 22.00 bsc .866? d1 20.00 bsc .787? e 22.00 bsc .866? e1 20.00 bsc .787? e 0.50 bsc .020? q 0 ? 7 0 ? 7 l 0.45 0.60 0.75 .018? .024? .030? l1 1.00 ref .039? ref tolerances of form and position ddd 0.08 .003? d1 d e l b a1 a l1 notes: 1. controlling dimension is millimeter. 2. dimensioning and tolerancing per asme y14.5m-1994. e1 e m b seating plane ddd b
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 35 10 revision history revision date changes a1 february, 2006 advance release. a2 june, 2006 updated part numbers for orderin g (tables 5 & 6), updated v oh and v ol specification to include the current load used for testing a3 july, 2006 updated part numbers for ordering (tables 5 & 6). updated text in sections 3 and 4. updated parameter descriptions in sections 5.1 and 5.3. updated tspickl, tspickh, and tspidov timing. corrected figure spi master timing to use ee_cs . added foot- note to xti table. remove d sclk/lrclk rela tive timing from dai port timing. removed sclk/lrclk slave relative timing from dao port timing. a4 october, 2007 updated the tspidsu, tspickl, and tspickh ti ming parameters fo r master mode spi. this applies to both spi ports. pp1 may, 2008 updated product feature list in ta b l e 2 . updated figure 19 and figure 21 . pp2 june, 2008 added typical crystal frequency values in table footnote 1 and minimum and maximum values of f xtal in section 5.8 . redefined master mode clock speed for scp_clk in section 5.11 . redefined dc leakage characterization data in section 5.3 , correcting units of measurement. modified footnote 1 under section 5.10 . pp3 september, 2008 removed references to external parallel flash / sram interface. pp4 june, 2009 updated product number references in section 5.9 , section 6 , section 7 , ta b l e 2 , . table 3 , and ta b l e 4 . for all active low pins, changed active low pin designation from ?#? character after the pin name to a line over the pin name as in ?ee_cs ?. removed active low designation from the bdi_req pin in the 128-pin pinout drawings in figure 19 and figure 20 , and in the 144-pin pinout drawings in figure 21 and figure 22 . updated the pin names referred to in the timing diagrams in figure 9 , figure 10 , figure 17 , and figure 18 . updated the parameters in section 5.15 . pp5 july, 2009 updated figure 19 , figure 20 , figure 21 . removed cs495314-cqz and cs495314-cqzr from table 5 and table 6 . added recommendation that cs4953x4 family be used with new designs. updated section 2 pp6 november, 2009 removed references to uart port. removed references to 11.2896, 18.432, and 27 mhz frequency clocks in note 1 in section 5.8 ?switching characteristics ? xti? on page 12 and the minimum and maximum external crystal operating frequency va lues in that same section. updated section 5.17 ?switching characterist ics ? digital audio output port? on page 24 . in figure 21, "144-pin lqfp pin-out drawing (cs495313)", on page 32 , moved scp2_sda from pin 106 to pin 105, deleted duplicate ee_cs from pin 25, and designated pin 140 bdi_req as active low. designated pin 32, bdi_req as active low in figure 19, "128-pin lqfp pin-out drawing (cs495303/cs495313)", on page 30 and in figure 20, "128-pin lqfp pin-out drawing (cs495304/cs495314)", on page 31 . in section 5.3 , the parameter, ?input leakage current (all digital pins with internal pull-up resistors enabled, and xti)?, max value changes from 50 a to 70 a. in section 5.13 , the parameter scp_cl k low to scp_sda out valid with symbol ?tiicdov? maximum valu e changes from 18 ns to 36 ns. pp7 june, 2010 updated table 5 to show status of various parts.
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 36 pp8 april, 2011 added tj conditions to section 5.2 . changed 500 ma to 350 ma in section 5.4 . removed references to dsd. updated legal statement. updated features list. added notes to section 5.10 . updated section 5.16 ?switching characteristics ? digital audio slave input port? on page 23 updated section 5.17 ?switching characteristics ? digital audio output port? on page 24 . pp9 august, 2011 in section section 5.9 , added max value of dclk frequency value in CS49530X-dvz and cs49531x-dvz to 130 mhz; added min value of dclk period in CS49530X-dvz and cs49531x-dvz to 7.7 ns. added notes to section 5.10 . updated figure 14. pp10 february, 2012 updated trademark information throughout document and boilerplate. updated max fdclk value for dvz parts to 131 mhz and min dclk value for dvz parts to 7.63 ns in section 5.9 . updated tspickl and tspickh minimum values in section 5.11 . added tdaisstlr and tdaislrts to section 5.16 . changed max spec of tdaosdv in section 5.17 . updated tsddh minimum value in section 5.18 . revision date changes
cs4953xx data sheet 32-bit audio decoder dsp family ds705f2 37 contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find the one nearest you, go to www.cirrus.com. important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtai n the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pe rtaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual propert y rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circui ts or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using se miconductor products may involv e potential risks of death, personal injury, or severe property or environmental damage (?critical applications?). cirrus products are not designed , authorized or warranted for use in products surgically implanted into the body, automotive safety or security de vices, life suppor t products or other critical applications. inclusion of cirrus products in such applicat ions is unders tood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permits the use of cirrus products in critical applications, cu stomer agrees, by such use, to fully indemnify cirrus, its office rs, directors, employees , distributors and other agents fr om any and all liability, including attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, cirrus logic logo designs, cirrus framework, and dsp condenser are trademarks of cirrus logic, inc. all o ther brand and product names in this document may be trademarks or service marks of their respective owners. thx is a registered trademark of thx, ltd. thx select 2 and thx ultra 2 are trademarks of thx, ltd. dolby, dolby digital, dolby headphone, virtual speaker, pro logic, audistry, and dolby volume are registered trademarks of dolb y laboratories, inc. aac, ac-3, dolby truehd, and dolby volume 258 are trademarks of dolby laboratories, inc. supply of an implementation of dolby technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of dolby laboratories, to use the implem entation in any finished end-user or ready- to-use final product. it is hereby notified that a lice nse for such use is required from dolby laboratories. dts and dts neo:6 are registered trademarks of the digital theater systems, inc. dts-es 96/24, dts-es, dts 6.1, dts 96/24, dts neural surround, and dts express are trademarks of digital theater systems, inc. it is hereby notified that a third-party license from dts is necessary to distribute software of dts in any finished end-user or ready-to-use final product. srs, srs 3d, srs cs auto, srs cs headphone, srs circle cinema 3d , srs circle surround, srs circle surround ii, srs geq, srs har dlimiter, srs headphone, srs headphone 360, srs hpf, srs studiosound hd, srs trueq, srs trumedia, srs trusurround, srs trusurround xt, srs tr usurround hd, srs trusurround hd4, srs truvolume, srs vip+, srs wow, srs wow xt, srs wow hd are either trademarks or registered trademarks of srs labs, inc. srs, srs 3d, srs cs auto, srs cs headphone, srs circle cinema 3d , srs circle surround, srs circle surround ii, srs geq, srs har dlimiter, srs headphone, srs headphone 360, srs hpf, srs studiosound hd, srs trueq, srs trumedia, srs trusurround, srs trusurround xt, srs tr usurround hd, srs trusurround hd4, srs truvolume, srs vip+, srs wow, srs wow xt, srs wow hd technologies are incorporated under license from srs labs, inc. srs, srs 3d, srs cs auto, srs cs headphone, srs circle cinema 3d , srs circle surround, srs circle surround ii, srs geq, srs har dlimiter, srs headphone, srs headphone 360, srs hpf, srs studiosound hd, srs trueq, srs trumedia, srs trusurround, srs trusurround xt, srs tr usurround hd, srs trusurround hd4, srs truvolume, srs vip+, srs wow, srs wow xt , srs wow hd technologies incorporated in the cirrus logic cs4 953xx products are owned by srs labs, a u.s. corporation and licensed to cirrus logic, inc. purchaser of cirrus logic cs4953xx products must s ign a license for use of the chip and display of the srs labs trademarks. any products incorporating the cirrus logic cs4953xx products must be sent to srs labs for review. srs, srs 3d, srs cs auto, srs cs headphone, srs circle cinema 3d, srs circle surr ound, srs circle surround ii, srs geq, srs hardlimiter, srs hea dphone, srs headphone 360, srs hpf, srs studio-sound hd, srs trueq, srs trumedia, sr s trusurround, srs trusurround xt, srs trusurround hd, srs trusur round hd4, srs truvolume, srs vip+, srs wow, srs wow xt, srs wow hd technologies are protected under us and foreign patents issued and/or pend ing. neither the purchase of the cirrus logic cs4953xx products, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any srs technology/solution. srs labs requires all set makers to comply with all rules and regulations as outlined in the srs trademark usage manual. motorola is a registered trademark of motorola, inc. spi is a trademark of motorola, inc. intel is a registered trademark of intel corporation. i 2 c is a trademark of philips semiconductor.

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